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ISP1161A1BD +BOM

Low Speed USB Controller

Produttore:

ST
ProduttorePart #:

ISP1161A1BD
Scheda dati:

ISP1161A1BD Scheda dati (PDF)
Feature-minimum-operating-supply-voltage-v:

3|4
Feature-maximum-operating-supply-voltage-v:

3.6|5.5
Feature-pin-count:

64
Feature-cecc-qualified:

No

ISP1161A1BD Descrizione generale

The ISP1161A1BD is a cutting-edge USB host controller IC that is perfect for a wide range of high-speed USB communication applications. With its USB 2.0 compliant interface and impressive data rates of up to 12 Mbps and 480 Mbps for full-speed and high-speed connections, this IC delivers exceptional performance. The built-in 6 KB FIFO buffer further enhances data transfer efficiency, making it ideal for demanding tasks. Additionally, its support for up to 127 USB devices and compatibility with low-speed and full-speed USB devices make it extremely versatile. The inclusion of USB On-The-Go (OTG) specification support also ensures seamless connectivity with mobile devices

Caratteristiche principali

Complies withUniversal Serial Bus Specification Rev. 2.0
The Host Controller portion of the ISP1161A1 supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
The Device Controller portion of the ISP1161A1 supports data transfer at full-speed (12 Mbit/s)
Combines the HC and the DC in a single chip
On-chip DC complies with most USB device class specifications
Both the HC and the DC can be accessed by an external microprocessor via separate I/O port addresses
Selectable one or two downstream ports for the HC and one upstream port for the DC
High-speed parallel interface to most of the generic microprocessors and Reduced Instruction Set Computer (RISC) processors such as:
Hitachi® SuperH™ SH-3 and SH-4
MIPS-based™ RISC
ARM7™, ARM9™, StrongARM®
Maximum 15 Mbyte/s data transfer rate between the microprocessor and the HC, 11.1 Mbyte/s data transfer rate between the microprocessor and the DC
Supports single-cycle and burst mode DMA operations
Up to 14 programmable USB endpoints with 2 fixed control IN/OUT endpoints for the DC
Built-in separate FIFO buffer RAM for the HC (4 kbytes) and DC (2462 bytes)
Endpoints with double buffering to increase throughput and ease real-time data transfer for both DC transfers and HC isochronous (ISO) transactions
6 MHz crystal oscillator with integrated PLL for low EMI
Controllable LazyClock (100 kHz±50 %) output during ‘suspend’
Clock output with programmable frequency (3 MHz to 48 MHz)
Software controlled connection to USB bus (SoftConnect) on upstream port for the DC
Good USB connection indicator that blinks with traffic (GoodLink) for the DC
Software selectable internal 15 kΩpull-down resistors for HC downstream ports
Dedicated pins for suspend sensing output and wake-up control input for flexible applications
Global hardware reset input pin and separate internal software reset circuits for HC and DC
Operation from a 5 V or a 3.3 V power supply
Operating temperature range−40°Cto+85°C
Available in two LQFP64 packages (SOT314-2 and SOT414-1).

Specifiche

feature-minimum-operating-supply-voltage-v	3\|4	feature-process-technology
feature-maximum-operating-supply-voltage-v	3.6\|5.5	feature-packaging
feature-rad-hard		feature-pin-count	64
feature-cecc-qualified	No	feature-esd-protection
feature-escc-qualified		feature-military	No
feature-aec-qualified		feature-aec-qualified-number
feature-auto-motive		feature-p-pap
feature-eccn-code		feature-svhc
feature-svhc-exceeds-threshold

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