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Vedi Specifiche Tecniche

74HC573PW,118 +BOM

2V~6V D-Typelocking Latch 8 14ns TSSOP-20 Latches ROHS

Produttore:

Nexperia
ProduttorePart #:

74HC573PW,118
Scheda dati:

74HC573PW,118 Scheda dati (PDF)
Type Number:

74HC573PW
VCC (V):

2.0 - 6.0
Logic Switching Levels:

CMOS
Output Drive Capability (mA):

± 7.8
EDA/CAD Modelli:

Richiedi modelli CAD gratuiti per 74HC573PW,118

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74HC573PW,118 Descrizione generale

The 74HC573; 74HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable () inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on causes the outputs to assume a high-impedance OFF-state. Operation of the input does not affect the state of the latches. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V.

Caratteristiche principali

Wide supply voltage range from 2.0 to 6.0 V
CMOS low power dissipation
High noise immunity
Input levels:For 74HC573: CMOS levelFor 74HCT573: TTL level
For 74HC573: CMOS level
For 74HCT573: TTL level
Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
Useful as input or output port for microprocessors and microcomputers
3-state non-inverting outputs for bus-oriented applications
Common 3-state output enable input
Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
Complies with JEDEC standards:JESD8C (2.7 V to 3.6 V)JESD7A (2.0 V to 6.0 V)
JESD8C (2.7 V to 3.6 V)
JESD7A (2.0 V to 6.0 V)
ESD protection:
HBM JESD22-A114F exceeds 2 kVMM JESD22-A115-A exceeds 200 V
HBM JESD22-A114F exceeds 2 kV
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from -40 °C to +85 °C and from -40 °C to +125 °C

Specifiche

Type number	74HC573PW	VCC (V)	2.0 - 6.0
Logic switching levels	CMOS	Output drive capability (mA)	± 7.8
tpd (ns)	14	Power dissipation considerations	low
Tamb (°C)	-40~125	Rth(j-a) (K/W)	100
Ψth(j-top) (K/W)	4.6	Rth(j-c) (K/W)	44.9
Packing	SOT360-1_118	Orderable part number	74HC573PW,118
Chemical content	74HC573PW

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AVAQ determina e confeziona tutti i dispositivi in base ai requisiti di protezione contro le scariche elettrostatiche (ESD) e il livello di sensibilità all'umidità (MSL)..