Questo sito web utilizza i cookie. Utilizzando questo sito, acconsenti all'utilizzo dei cookie. Per ulteriori informazioni, dai un'occhiata al nostro politica sulla riservatezza.

Le immagini servono solo come riferimento,

Vedi Specifiche Tecniche

W972GG6JB-25 +BOM

Winbond Electronics Corporation's W972GG6JB-25 product overview

Produttore:

Winbond Electronics
ProduttorePart #:

W972GG6JB-25
Scheda dati:

W972GG6JB-25 Scheda dati (PDF)
Part Life Cycle Code:

Obsolete
Reach Compliance Code:

compliant
ECCN Code:

EAR99
HTS Code:

8542.32.00.36
EDA/CAD Modelli:

Richiedi modelli CAD gratuiti per W972GG6JB-25

E-mail: [email protected]

Skype: live:.cid.ab6b29428937b76

tel: +852 95804164

W972GG6JB-25 Descrizione generale

Winbond's W972GG6JB-25 chip is a robust microcontroller designed to meet the demands of modern embedded systems. Its 80MHz operating frequency enables high-speed processing, while the 256KB of flash memory and 32KB of RAM provide ample storage and memory for complex applications. With communication interfaces such as UART, I2C, SPI, and USB, this chip offers versatility and compatibility with a variety of devices. Whether used in industrial automation, consumer electronics, or other applications, the W972GG6JB-25 delivers reliable performance and seamless connectivity

Caratteristiche principali

Power Supply: VDD, VDDQ = 1.8 V ± 0.1V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and CLK )
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges of DQS
Posted CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 84 Ball (11X13 mm2), using Lead free materials with RoHS compliant

Specifiche

Part Life Cycle Code	Obsolete	Reach Compliance Code	compliant
ECCN Code	EAR99	HTS Code	8542.32.00.36
Access Mode	MULTI BANK PAGE BURST	Access Time-Max	0.4 ns
Additional Feature	AUTO/SELF REFRESH	Clock Frequency-Max (fCLK)	400 MHz
I/O Type	COMMON	Interleaved Burst Length	4,8
JESD-30 Code	R-PBGA-B84	Length	13 mm
Memory Density	2147483648 bit	Memory IC Type	DDR2 DRAM
Memory Width	16	Number of Functions	1
Number of Ports	1	Number of Terminals	84
Number of Words	134217728 words	Number of Words Code	128000000
Operating Mode	SYNCHRONOUS	Operating Temperature-Max	85 °C
Operating Temperature-Min		Organization	128MX16
Output Characteristics	3-STATE	Qualification Status	Not Qualified
Refresh Cycles	8192	Seated Height-Max	1.2 mm
Self Refresh	YES	Sequential Burst Length	4,8
Standby Current-Max	0.012 A	Supply Current-Max	0.25 mA
Supply Voltage-Max (Vsup)	1.9 V	Supply Voltage-Min (Vsup)	1.7 V
Supply Voltage-Nom (Vsup)	1.8 V	Surface Mount	YES
Technology	CMOS	Temperature Grade	OTHER
Terminal Form	BALL	Terminal Pitch	0.8 mm
Terminal Position	BOTTOM	Width	11 mm

Politiche di servizio e altro

Relativi al servizio post-vendita e alla liquidazione

Pagamento

Metodo di pagamento

TT/bonifico bancario

PayPal

Western Union

Grammo dei soldi

Per canali di pagamento alternativi, contattaci a:

[email protected]

Spedizione e imballaggio

metodo di spedizione

Fedex

UPS

DHL

NTN

Imballaggio

AVAQ determina e confeziona tutti i dispositivi in base ai requisiti di protezione contro le scariche elettrostatiche (ESD) e il livello di sensibilità all'umidità (MSL)..