Questo sito web utilizza i cookie. Utilizzando questo sito, acconsenti all'utilizzo dei cookie. Per ulteriori informazioni, dai un'occhiata al nostro Privacy Policy.

Le immagini servono solo come riferimento,

Vedi Specifiche Tecniche

SN65LVDT33D

Quad LVDS receiver with -4 to 5-V common-mode range

Produttore:

Texas Instruments, Inc
ProduttorePart #:

SN65LVDT33D
Scheda dati:

SN65LVDT33D Scheda dati (PDF)
Function:

Receiver
Protocols:

LVDS
Number of transmitters:

0
Number of receivers:

4
EDA/CAD Modelli:

Richiedi modelli CAD gratuiti per SN65LVDT33D

E-mail: [email protected]

Skype: live:.cid.ab6b29428937b76

tel: +852 95804164

SN65LVDT33D Descrizione generale

This family of four LVDS data line receivers offers the widest common-mode input voltage range in the industry. These receivers provide an input voltage range specification compatible with a 5-V PECL signal as well as an overall increased ground-noise tolerance. They are in industry standard footprints with integrated termination as an option.

Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input voltage hysteresis to improve noise rejection on slowly changing input signals. The input thresholds are still no more than ±50 mV over the full input common-mode voltage range.

The high-speed switching of LVDS signals usually necessitates the use of a line impedance matching resistor at the receiving-end of the cable or transmission media. The SN65LVDT series of receivers eliminates this external resistor by integrating it with the receiver. The nonterminated SN65LVDS series is also available for multidrop or other termination circuits.

The receivers can withstand ±15 kV human-body model (HBM) and ±600 V machine model (MM) electrostatic discharges to the receiver input pins with respect to ground without damage. This provides reliability in cabled and other connections where potentially damaging noise is always a threat.

The receivers also include a (patent pending) failsafe circuit that will provide a high-level output within 600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted lines, or powered-down transmitters. The failsafe circuit prevents noise from being received as valid data under these fault conditions. This feature may also be used for Wired-Or bus signaling. See The Active Failsafe Feature of the SN65LVDS32B application note.

The intended application and signaling technique of these devices is point-to-point baseband data transmission over controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The SN65LVDS33, SN65LVDT33, SN65LVDS34 and SN65LVDT34 are characterized for operation from 40°C to 85°C.

Caratteristiche principali

400-Mbps Signaling Rate¹ and 200-Mxfr/s Data Transfer Rate
Operates With a Single 3.3-V Supply
–4-V to 5-V Common-Mode Input Voltage Range
Differential Input Thresholds <±50 mV With 50 mV of Hysteresis Over Entire Common-Mode Input Voltage Range
Integrated 110- Line Termination Resistors On LVDT Products
TSSOP Packaging (33 Only)
Complies With TIA/EIA-644 (LVDS)
Active Failsafe Assures a High-Level Output With No Input
Bus-Pin ESD Protection Exceeds 15 kV HBM
Input Remains High-Impedance on Power Down
TTL Inputs Are 5-V Tolerant
Pin-Compatible With the AM26LS32, SN65LVDS32B, µA9637, SN65LVDS9637B

¹ The signaling rate of a line, is the number of voltage transitions that are made per second expressed in the units bps (bits per second).

Specifiche

Function	Receiver	Protocols	LVDS
Number of transmitters	0	Number of receivers	4
Supply voltage (V)	3.3	Signaling rate (MBits)	400
Input signal	ECL, LVPECL, PECL	Output signal	LVTTL
Rating	Catalog	Operating temperature range (°C)	-40 to 85
feature-function	Receiver	feature-number-of-drivers	0
feature-number-of-receivers	4	feature-number-of-elements-per-chip	2
feature-transmission-data-rate-mbps	400	feature-maximum-propagation-delay-time-ns	9
feature-input-signal-type	ECL\|LVPECL\|PECL	feature-differential-input-low-threshold-voltage-v	-0.05(Min)
feature-differential-input-high-threshold-voltage-v	0.05(Max)	feature-maximum-differential-output-voltage-v
feature-maximum-input-current-ua	150	feature-supplier-temperature-grade
feature-packaging	Tube	feature-rad-hard
feature-pin-count	16	feature-cecc-qualified	No
feature-esd-protection		feature-escc-qualified
feature-military	No	feature-aec-qualified	No
feature-aec-qualified-number		feature-eccn-code	EAR99
feature-svhc	No	feature-svhc-exceeds-threshold	No

Politiche di servizio e altro

Relativi al servizio post-vendita e alla liquidazione

Pagamento

Metodo di pagamento

TT/bonifico bancario

PayPal

Western Union

Grammo dei soldi

Per canali di pagamento alternativi, contattaci a:

[email protected]

Spedizione e imballaggio

metodo di spedizione

Fedex

UPS

DHL

NTN

Imballaggio

AVAQ determina e confeziona tutti i dispositivi in base ai requisiti di protezione contro le scariche elettrostatiche (ESD) e il livello di sensibilità all'umidità (MSL)..