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CLOCK RECOVERY AND SYNTHESIS UNIT
PLCCProduttore:
ProduttorePart #:
S3014D-6
Scheda dati:
Launch_date:
Jun 2, 1997
Last_inspection_date:
+90
Supplier_cage_code:
55NN2
Htsusa:
8542390001
EDA/CAD Modelli:
Invia tutte le distinte materiali a
[email protected],
oppure compila il modulo sottostante per un preventivo su S3014D-6. Risposta garantita entro
12hr.
Compila il breve modulo sottostante e ti forniremo immediatamente il preventivo.
The function of the S3014 clock synthesis and recovery unit is to derive high speed timing signals for SONET/SDH-based equipment. The S3014 is implemented using AMCC's proven Phase Locked Loop(PLL) technology.In Clock Recovery mode, the S3014 receives either an STS-3/STM-1 or STS-12/STM-4 scrambled NRZ signal and recovers the clock from the data. The chip outputs a differential ECL bit clock and retimed data.In Clock Synthesis mode, the S3014 receives a 19.44,51.84, or 155.52 MHz reference clock and outputs an STS-3/STM-1 or STS-12/STM-4 differential ECL clock.The S3014 utilizes an on-chip PLL which consists of a phase detector,a loop filter, and a voltage controlled oscillator (VCO). The phase detector compares the phase relationship between the VCO output and the REFCLK input,a loop filter converts the phase detector output into a smooth DC voltage, and the DC voltage is input to the VCO whose frequency is varied by this voltage.A block diagram is shown in Figure 1.
place | launch_date | Jun 2, 1997 | |
last_inspection_date | +90 | supplier_cage_code | 55NN2 |
htsusa | 8542390001 | schedule_b | 8542390000 |
ppap | aec | ||
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AVAQ determina e confeziona tutti i dispositivi in base ai requisiti di protezione contro le scariche elettrostatiche (ESD) e il livello di sensibilità all'umidità (MSL)..
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