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Boosts Hz input clock by a factor of with pin SOIC packa
SOP-8Produttore:
ProduttorePart #:
PL123-05NSI
Scheda dati:
Type:
Fanout Buffer (Distribution)
Number Of Circuits:
1
Ratio - InputOutput:
1:5
Differential - InputOutput:
No/No
EDA/CAD Modelli:
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The PL123-05/-09 (-05H/-09H for High Drive) are high performance, low skew, low jitter zero delay buffers designed to distribute high speed clocks. They have one (PL123-05) or two (PL123-09) low-skew output banks, of 4 outputs each, that are synchronized with the input. The PL123-09 allows control of the banks of outputs by using the S1 and S2 inputs as shown in the Selector Definition table on page 2 of the datasheet.The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than ±100ps, the device acts as a zero delay buffer. The input output propagation delay can be advanced or delayed by adjusting the load on the CLKOUT pin.These parts are not intended for 5V input-tolerant applications.
Category | Integrated Circuits (ICs)Clock/TimingClock Buffers, Drivers | Series | - |
Type | Fanout Buffer (Distribution) | Number of Circuits | 1 |
Ratio - Input:Output | 1:5 | Differential - Input:Output | No/No |
Input | CMOS | Output | CMOS |
Frequency - Max | 134 MHz | Voltage - Supply | 1.62V ~ 3.63V |
Operating Temperature | -40°C ~ 85°C | Mounting Type | Surface Mount |
Base Product Number | PL123 |
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