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Vedi Specifiche Tecniche

M38510/05754BEA +BOM

CMOS 8-Stage Static Shift Register

Produttore:

Texas Instruments, Inc
ProduttorePart #:

M38510/05754BEA
Scheda dati:

M38510/05754BEA Scheda dati (PDF)
Configuration:

Universal
Bits (#):

8
Technology Family:

CD4000
Supply Voltage (min) (V):

3
EDA/CAD Modelli:

Richiedi modelli CAD gratuiti per M38510/05754BEA

M38510/05754BEA Descrizione generale

CD4014B and CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel "JAM" inputs to each register stage. Each register stage is D-type, master-slave flip-flop. In addition to an output form stage 8, "Q" outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014B. In the CD4021B serial entry is synchronous with the clock by parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021B, the CLOCK input of the internal stage is "forced" when asynchronous parallel entry is made. Register expansion using multiple packages is permitted.

The CD4014B and CD4021B series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-oultine packages (PW and PWR suffixes).

Caratteristiche principali

Medium speed operation…12 MHz (typ.) clock rate at V_DD – V_SS = 10 V
Fully static operation
8 master-slave flip-flops plus output buffering and control gating
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (full package-temperature range) =
1 V at V_DD = 5 V
2 V at V_DD = 10 V
2.5 V at V_DD = 15 V
Standardized, symmetrical output characteristics
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
Applications:
- Parallel input/serial output data queueing
- Parallel to serial data conversion
- General-purpose register

Data sheet acquired from Harris Semiconductor

Specifiche

Configuration	Universal	Bits (#)	8
Technology family	CD4000	Supply voltage (min) (V)	3
Supply voltage (max) (V)	18	Input type	Standard CMOS
Output type	Push-Pull	Clock frequency (MHz)	8.5
IOL (max) (mA)	4.2	IOH (max) (mA)	-4.2
Supply current (max) (µA)	3000	Features	Balanced outputs, Positive input clamp diode, Standard speed (tpd > 50ns)
Operating temperature range (°C)	-55 to 125	Rating	Military
feature-type		feature-logic-family	CD4000
feature-logic-function	Shift Register	feature-operation-mode	Serial/Parallel to Serial
feature-number-of-elements-per-chip	1	feature-number-of-element-inputs	9
feature-number-of-element-outputs	3	feature-number-of-stages	8
feature-direction-type	Uni-Directional	feature-triggering-type	Positive-Edge
feature-process-technology	CMOS	feature-output-type
feature-minimum-operating-supply-voltage-v	3	feature-maximum-operating-supply-voltage-v	18
feature-tolerant-i-os-v		feature-packaging	Tube
feature-rad-hard	No	feature-pin-count	16
feature-cecc-qualified	No	feature-esd-protection
feature-escc-qualified		feature-military
feature-aec-qualified	No	feature-aec-qualified-number
feature-auto-motive	No	feature-p-pap	No
feature-eccn-code	EAR99	feature-svhc	Yes
feature-svhc-exceeds-threshold	No

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