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Vedi Specifiche Tecniche

LSI53C895A +BOM

Efficient and cost-effective bus controller solutio

Produttore:

Lsi Corporation
ProduttorePart #:

LSI53C895A
Scheda dati:

LSI53C895A Scheda dati (PDF)
Part Life Cycle Code:

Obsolete
Pin Count:

208
ECCN Code:

3A991.A.2
HTS Code:

8542.31.00.01
EDA/CAD Modelli:

Richiedi modelli CAD gratuiti per LSI53C895A

Caratteristiche principali

Second Generation SuperWIDE HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC DEVICE
— 3.3V Power Supply
— User Selectable 3.3V/2.5V I/O
— 18000 PLD Gates / 384 Macrocells
— Up to 192 I/O Pins
— 384 Registers
— High-Speed Global Interconnect
— SuperWIDE Generic Logic Block (32 Macrocells) for Optimum Performance
— SuperWIDE Input Gating (68 Inputs) for Fast Counters, State Machines, Address Decoders, etc.
— PCB Efficient Ball Grid Array (BGA) Package Options
— Interfaces with Standard 5V TTL Devices
HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 165 MHz Maximum Operating Frequency
— tpd = 6.0 ns Propagation Delay
— TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels
— Electrically Erasable and Reprogrammable
— Non-Volatile
— Programmable Speed/Power Logic Path Optimization
IN-SYSTEM PROGRAMMABLE
— Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality
— Reprogram Soldered Devices for Faster Debugging
100% IEEE 1149.1 BOUNDARY SCAN TESTABLE AND 3.3V IN-SYSTEM PROGRAMMABLE
ARCHITECTURE FEATURES
— Enhanced Pin-Locking Architecture with SingleLevel Global Routing Pool and SuperWIDE GLBs
— Wrap Around Product Term Sharing Array Supports up to 35 Product Terms Per Macrocell
— Macrocells Support Concurrent Combinatorial and Registered Functions
— Macrocell Registers Feature Multiple Control Options Including Set, Reset and Clock Enable
— Four Dedicated Clock Input Pins Plus Macrocell Product Term Clocks
— Programmable I/O Supports Programmable Bus Hold, Pull-up, Open Drain and Slew Rate Options
— Four Global Product Term Output Enables, Two Global OE Pins and One Product Term OE per Macrocell

Specifiche

Part Life Cycle Code	Obsolete	Pin Count	208
ECCN Code	3A991.A.2	HTS Code	8542.31.00.01
Address Bus Width	32	Clock Frequency-Max	40 MHz
External Data Bus Width	32	JESD-30 Code	S-PQFP-G208
Length	28 mm	Number of Terminals	208
Operating Temperature-Max	70 °C	Qualification Status	Not Qualified
Seated Height-Max	4.1 mm	Supply Voltage-Max	3.63 V
Supply Voltage-Min	2.97 V	Surface Mount	YES
Technology	CMOS	Temperature Grade	COMMERCIAL
Terminal Form	GULL WING	Terminal Pitch	0.5 mm
Terminal Position	QUAD	Width	28 mm
uPs/uCs/Peripheral ICs Type	BUS CONTROLLER, SCSI

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