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LCMXO2-4000HC-4MG132C +BOM

LCMXO2-4000HC-4MG132C

Produttore:

Lattice Semiconductor Corporation
ProduttorePart #:

LCMXO2-4000HC-4MG132C
Scheda dati:

LCMXO2-4000HC-4MG132C Scheda dati (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
ECCN Code:

EAR99
EDA/CAD Modelli:

Richiedi modelli CAD gratuiti per LCMXO2-4000HC-4MG132C

LCMXO2-4000HC-4MG132C Descrizione generale

Lattice Semiconductor's LCMXO2-4000HC-4MG132C CPLD offers a compelling combination of performance, flexibility, and efficiency. With its 4,000 LUT capacity, non-volatile configuration memory, and low-power operation at 1.2V, this FPGA is well-suited for diverse applications. Housed in a 132-pin Micro FineLine BGA package, it enables compact designs and efficient signal routing, while its mix of general-purpose I/O pins and specialized interfaces like LVCMOS and LVDS provide versatility in interfacing with external components

Caratteristiche principali

Flexible Logic Architecture
Six devices with 256 to 6864 LUT4s and 19 to 335 I/Os
Ultra Low Power Devices
Advanced 65 nm low power process
As low as 19 µW standby power
Programmable low swing differential I/Os
Stand-by mode and other power saving options
Embedded and Distributed Memory
Up to 240 Kbits sysMEM™ Embedded Block RAM
Up to 54 Kbits Distributed RAM
Dedicated FIFO control logic On-Chip User Flash Memory
Up to 256 Kbits of User Flash Memory
100,000 write cycles
Accessible through WISHBONE, SPI, I2C and JTAG interfaces
Can be used as soft processor PROM or as Flash memory
Pre-Engineered Source Synchronous I/O
DDR registers in I/O cells
Dedicated gearing logic
7:1 Gearing for Display I/Os
Generic DDR, DDRX2, DDRX4
Dedicated DDR/DDR2/LPDDR memory with DQS support
High Performance, Flexible I/O Buffer
Programmable sysIO™ buffer supports wide range of interfaces:
– LVCMOS 3.3/2.5/1.8/1.5/1.2
– LVTTL
–PCI
– LVDS, Bus-LVDS, MLVDS, RSDS, LVPECL
– SSTL 25/18
– HSTL 18
– Schmitt trigger inputs, up to 0.5V hysteresis
I/Os support hot socketing
On-chip differential termination
Programmable pull-up or pull-down mode

Specifiche

Pbfree Code	Yes	Part Life Cycle Code	Active
Reach Compliance Code	compliant	ECCN Code	EAR99
HTS Code	8542.39.00.01	Additional Feature	ALSO OPERATES AT 3.3 V NOMINAL SUPPLY
JESD-30 Code	S-PBGA-B132	JESD-609 Code	e1
Length	8 mm	Moisture Sensitivity Level	3
Number of Inputs	104	Number of Logic Cells	4320
Number of Outputs	104	Number of Terminals	132
Operating Temperature-Max	85 °C	Operating Temperature-Min
Packing Method	TRAY	Peak Reflow Temperature (Cel)	250
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Seated Height-Max	1.35 mm	Supply Voltage-Max	3.465 V
Supply Voltage-Min	2.375 V	Supply Voltage-Nom	2.5 V
Surface Mount	YES	Temperature Grade	OTHER
Terminal Finish	Tin/Silver/Copper (Sn/Ag/Cu)	Terminal Form	BALL
Terminal Pitch	0.5 mm	Terminal Position	BOTTOM
Time@Peak Reflow Temperature-Max (s)	30	Width	8 mm

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