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LCMXO1200C-5TN144C +BOM

FPGA with 1200 LUTs and 113 I/O

Produttore:

LATTICE SEMICONDUCTOR CORP
ProduttorePart #:

LCMXO1200C-5TN144C
Scheda dati:

LCMXO1200C-5TN144C Scheda dati (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Pin Count:

144
Reach Compliance Code:

compliant
EDA/CAD Modelli:

Richiedi modelli CAD gratuiti per LCMXO1200C-5TN144C

E-mail: [email protected]

Skype: live:.cid.ab6b29428937b76

tel: +852 95804164

LCMXO1200C-5TN144C Descrizione generale

Featuring a speed grade of 5, the LCMXO1200C-5TN144C FPGA stands out for its high performance and flexibility. This FPGA is equipped with 1200 LUTs and 30 Kbits of embedded RAM, providing designers with ample programmable logic resources for implementing complex functions such as communication protocols and signal processing. The device's dedicated I/O pins allow for seamless interfacing with external devices, enhancing its connectivity options. Moreover, the LCMXO1200C-5TN144C supports low-power operation, making it suitable for applications that require energy efficiency. Designers can take advantage of Lattice's design tools and IP cores to expedite the development process and optimize the performance of their FPGA-based systems

Caratteristiche principali

Non-volatile, Infinitely Reconfigurable
Instant-on – powers up in microseconds
Single chip, no external configuration memory
required
Excellent design security, no bit stream to
intercept
Reconfigure SRAM based logic in milliseconds
SRAM and non-volatile memory programmable
through JTAG port
Supports background programming of
non-volatile memory
Sleep Mode
Allows up to 100x static current reduction
TransFR™ Reconfiguration (TFR)
In-field logic update while system operates
High I/O to Logic Density
256 to 2280 LUT4s
73 to 271 I/Os with extensive package options
Density migration supported
Lead free/RoHS compliant packaging
Embedded and Distributed Memory
Up to 27.6 Kbits sysMEM™ Embedded Block
RAM
Up to 7.5 Kbits distributed RAM
Dedicated FIFO control logic
Flexible I/O Buffer
Programmable sysIO™ buffer supports wide
range of interfaces:
− LVCMOS 3.3/2.5/1.8/1.5/1.2
− LVTTL
− PCI
− LVDS, Bus-LVDS, LVPECL, RSDS
sysCLOCK™ PLLs
Up to two analog PLLs per device
Clock multiply, divide, and phase shifting
System Level Support
IEEE Standard 1149.1 Boundary Scan
Onboard oscillator
Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
power supply
IEEE 1532 compliant in-system programming

Specifiche

Pbfree Code	Yes	Part Life Cycle Code	Active
Pin Count	144	Reach Compliance Code	compliant
ECCN Code	EAR99	HTS Code	8542.39.00.01
JESD-30 Code	S-PQFP-G144	JESD-609 Code	e3
Length	20 mm	Moisture Sensitivity Level	3
Number of CLBs	150	Number of Inputs	113
Number of Logic Cells	1200	Number of Outputs	113
Number of Terminals	144	Operating Temperature-Max	85 °C
Operating Temperature-Min		Organization	150 CLBS
Peak Reflow Temperature (Cel)	260	Power Supplies	1.8/3.3 V
Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY	Qualification Status	Not Qualified
Seated Height-Max	1.6 mm	Supply Voltage-Max	3.465 V
Supply Voltage-Min	1.71 V	Supply Voltage-Nom	1.8 V
Surface Mount	YES	Temperature Grade	OTHER
Terminal Finish	MATTE TIN	Terminal Form	GULL WING
Terminal Pitch	0.5 mm	Terminal Position	QUAD
Time@Peak Reflow Temperature-Max (s)	40	Width	20 mm

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