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LCMXO1200C-3FTN256C +BOM

Field Programmable Gate Array for customizable applications

Produttore:

Lattice Semiconductor Corporation
ProduttorePart #:

LCMXO1200C-3FTN256C
Scheda dati:

LCMXO1200C-3FTN256C Scheda dati (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Pin Count:

256
Reach Compliance Code:

compliant
EDA/CAD Modelli:

Richiedi modelli CAD gratuiti per LCMXO1200C-3FTN256C

LCMXO1200C-3FTN256C Descrizione generale

Lattice Semiconductor's LCMXO1200C-3FTN256C FPGA is the perfect choice for cost-sensitive applications that demand high performance and low power consumption. With 1200 LUTs, 64 Kbit Embedded Block RAM, and 18 I/O pins, this FPGA offers the flexibility and connectivity needed for industrial control systems, consumer electronics, automotive infotainment, and communication equipment. Its compact 256-pin TQFP package makes it suitable for space-constrained designs, while its maximum frequency of 75 MHz ensures efficient operation. Plus, with a supply voltage of 1.2V, this FPGA is designed for low power consumption, making it an excellent choice for a wide range of applications

Caratteristiche principali

Non-volatile, Infinitely Reconfigurable
Instant-on – powers up in microseconds
Single chip, no external configuration memory
required
Excellent design security, no bit stream to
intercept
Reconfigure SRAM based logic in milliseconds
SRAM and non-volatile memory programmable
through JTAG port
Supports background programming of
non-volatile memory
Sleep Mode
Allows up to 100x static current reduction
TransFR™ Reconfiguration (TFR)
In-field logic update while system operates
High I/O to Logic Density
256 to 2280 LUT4s
73 to 271 I/Os with extensive package options
Density migration supported
Lead free/RoHS compliant packaging
Embedded and Distributed Memory
Up to 27.6 Kbits sysMEM™ Embedded Block
RAM
Up to 7.5 Kbits distributed RAM
Dedicated FIFO control logic
Flexible I/O Buffer
Programmable sysIO™ buffer supports wide
range of interfaces:
− LVCMOS 3.3/2.5/1.8/1.5/1.2
− LVTTL
− PCI
− LVDS, Bus-LVDS, LVPECL, RSDS
sysCLOCK™ PLLs
Up to two analog PLLs per device
Clock multiply, divide, and phase shifting
System Level Support
IEEE Standard 1149.1 Boundary Scan
Onboard oscillator
Devices operate with 3.3V, 2.5V, 1.8V or 1.2V
power supply
IEEE 1532 compliant in-system programming

Specifiche

Pbfree Code	Yes	Part Life Cycle Code	Active
Pin Count	256	Reach Compliance Code	compliant
ECCN Code	3A991.D	HTS Code	8542.39.00.01
JESD-30 Code	S-PBGA-B256	JESD-609 Code	e1
Length	17 mm	Moisture Sensitivity Level	3
Number of CLBs	150	Number of Inputs	211
Number of Logic Cells	1200	Number of Outputs	211
Number of Terminals	256	Operating Temperature-Max	85 °C
Operating Temperature-Min		Organization	150 CLBS
Peak Reflow Temperature (Cel)	260	Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY
Qualification Status	Not Qualified	Seated Height-Max	1.7 mm
Supply Voltage-Max	3.465 V	Supply Voltage-Min	1.71 V
Supply Voltage-Nom	1.8 V	Surface Mount	YES
Temperature Grade	OTHER	Terminal Finish	Tin/Silver/Copper (Sn96.5Ag3.0Cu0.5)
Terminal Form	BALL	Terminal Pitch	1 mm
Terminal Position	BOTTOM	Time@Peak Reflow Temperature-Max (s)	40
Width	17 mm

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