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EP20K200BC356-1X +BOM
The EP20K200BC356-1X is a member of the FPGA APEX 20K Family, boasting 200K gates and 8320 cells
BGA-356-
Produttore:
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ProduttorePart #:
EP20K200BC356-1X
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Scheda dati:
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Part Life Cycle Code:
Obsolete
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Reach Compliance Code:
compliant
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ECCN Code:
3A991.D
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HTS Code:
8542.39.00.01
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EDA/CAD Modelli:
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EP20K200BC356-1X Descrizione generale
Altera's EP20K200BC356-1X, a member of the APEX 20K family, is a versatile programmable logic device offering a logic capacity of 200,000 logic elements. This high density allows for the implementation of complex digital circuits and systems on a single chip, making it an ideal choice for applications that demand substantial logic capability. With a system speed reaching several hundred MHz, this device ensures high-speed data processing and operations, supporting a wide range of applications including communications, data processing, and industrial control systems. Its 356 input/output pins and 356-pin BGA package enable extensive interaction and efficient heat dissipation, making it a flexible and reliable solution for hardware design. The EP20K200BC356-1X is programmable via standard programming languages for FPGAs, allowing for flexible and customizable hardware designs tailored to specific application requirements
Caratteristiche principali
- Configuration devices for SRAM-based LUT devices offer the following
- features:
- Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices
- Easy-to-use four-pin interface
- Low current during configuration and near-zero standby mode current
- Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
- Available in compact plastic packages
- 8-pin plastic dual in-line (PDIP) package
- 20-pin plastic J-lead chip carrier (PLCC) package
- 32-pin plastic thin quad flat pack (TQFP) package
- EPC2 device has reprogrammable flash configuration memory
- 5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.
- 1149.1 JTAG interface
- Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
- Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable
- Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices
- nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration
Specifiche
Part Life Cycle Code | Obsolete | Reach Compliance Code | compliant |
ECCN Code | 3A991.D | HTS Code | 8542.39.00.01 |
JESD-30 Code | S-PBGA-B356 | JESD-609 Code | e0 |
Length | 35 mm | Moisture Sensitivity Level | 3 |
Number of Dedicated Inputs | 4 | Number of I/O Lines | 277 |
Number of Inputs | 271 | Number of Logic Cells | 8320 |
Number of Outputs | 271 | Number of Terminals | 356 |
Operating Temperature-Max | 85 °C | Operating Temperature-Min | |
Organization | 4 DEDICATED INPUTS, 277 I/O | Output Function | MACROCELL |
Power Supplies | 2.5,2.5/3.3 V | Programmable Logic Type | LOADABLE PLD |
Propagation Delay | 2.5 ns | Qualification Status | Not Qualified |
Seated Height-Max | 1.63 mm | Supply Voltage-Max | 2.625 V |
Supply Voltage-Min | 2.375 V | Supply Voltage-Nom | 2.5 V |
Surface Mount | YES | Technology | CMOS |
Temperature Grade | OTHER | Terminal Finish | TIN LEAD |
Terminal Form | BALL | Terminal Pitch | 1.27 mm |
Terminal Position | BOTTOM | Width | 35 mm |
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