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Vedi Specifiche Tecniche

EP1S40F780C5 +BOM

Contains 41250 logic cells

Produttore:

Intel
ProduttorePart #:

EP1S40F780C5
Scheda dati:

EP1S40F780C5 Scheda dati (PDF)
Series:

Stratix®
Programmabe:

Not Verified
Number Of LABs/CLBs:

4125
Number Of Logic Elements/Cells:

41250
EDA/CAD Modelli:

Richiedi modelli CAD gratuiti per EP1S40F780C5

EP1S40F780C5 Descrizione generale

The EP1S40F780C5 FPGA, belonging to the esteemed Stratix family, stands out for its impressive logic density, as indicated by the 40,000 logic elements it encompasses. Its speed grade, represented by "F780", signifies its ability to reliably operate at a maximum frequency under specific conditions, providing varying performance levels to cater to diverse needs. Furthermore, the C5 package in which it is housed dictates its physical characteristics, ensuring seamless integration into circuit boards

Caratteristiche principali

Configuration devices for SRAM-based LUT devices offer the following
features:
Configures Altera ACEX 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K (including FLEX 10KE and FLEX 10KA) Mercury, Stratix, Stratix GX, Stratix II, and Stratix II GX devices
Easy-to-use four-pin interface
Low current during configuration and near-zero standby mode current
Programming support with the Altera Programming Unit (APU) and programming hardware from Data I/O, BP Microsystems, and other third-party programmers
Available in compact plastic packages
8-pin plastic dual in-line (PDIP) package
20-pin plastic J-lead chip carrier (PLCC) package
32-pin plastic thin quad flat pack (TQFP) package
EPC2 device has reprogrammable flash configuration memory
5.0-V and 3.3-V in-system programmability (ISP) through the built-in IEEE Std.
1149.1 JTAG interface
Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1
Supports programming through Serial Vector Format File (.svf), Jam Standard Test and Programming Language (STAPL) Format File (.jam), JAM Byte Code File (.jbc), and the Quartus II and MAX+PLUS II softwares using the USB-Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV download cable
Supports programming through Programmer Object File (.pof) for EPC1 and EPC1441 devices
nINIT_CONF pin allows INIT_CONF JTAG instruction to begin FPGA configuration

Specifiche

Series	Stratix®	Programmabe	Not Verified
Number of LABs/CLBs	4125	Number of Logic Elements/Cells	41250
Total RAM Bits	3423744	Number of I/O	615
Voltage - Supply	1.425V ~ 1.575V	Mounting Type	Surface Mount
Operating Temperature	0°C ~ 85°C (TJ)	Base Product Number	EP1S40

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