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A3PE600-1PQG208I +BOM

Field-programmable gate array with high capacity for customization

Produttore:

Microsemi Corporation
ProduttorePart #:

A3PE600-1PQG208I
Scheda dati:

A3PE600-1PQG208I Scheda dati (PDF)
Series:

ProASIC3E
Programmable:

Not Verified
Total RAM Bits:

110592
Number Of I/O:

147
EDA/CAD Modelli:

Richiedi modelli CAD gratuiti per A3PE600-1PQG208I

A3PE600-1PQG208I Descrizione generale

Microsemi Corporation's A3PE600-1PQG208I FPGA is a standout performer in the ProASIC3E family, offering 600,000 system gates, 2400 kb of RAM, and 288 I/O pins for high-performance and low-power consumption in a wide range of embedded systems and control applications. Its core voltage of 1.5V and I/O voltage range of 1.5V to 3.3V, coupled with a speed grade of -1, further emphasize its efficiency and reliability. The FPGA's emphasis on security and reliability, with support for advanced encryption standard (AES) and secure authentication, makes it an ideal choice for industrial and automotive applications, ensuring data integrity and confidentiality. Housed in a 208-pin plastic quad flat pack (PQFP) package, the A3PE600-1PQG208I is designed for easy integration and offers designers a versatile and reliable solution for implementing complex logic functions in their electronic designs

Caratteristiche principali

High Capacity
600 k to 3 Million System Gates
108 to 504 kbits of True Dual-Port SRAM
Up to 620 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
On-Chip User Nonvolatile Memory
1 kbit of FlashROM with Synchronous Interfacing
High Performance
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI
In-System Programming (ISP) and Security
ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption via JTAG (IEEE 1532–compliant)
FlashLock® Designed to Secure FPGA Contents
Low Power
Core Voltage for Low Power
Support for 1.5-V-Only Systems
Low-Impedance Flash Switches
High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure
Ultra-Fast Local and Long-Line Network
Enhanced High-Speed, Very-Long-Line Network
High-Performance, Low-Skew Global Network
Architecture Supports Ultra-High Utilization
Pro (Professional) I/O
700 Mbps DDR, LVDS-Capable I/Os
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 8 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS
Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL 2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3 Class I and II
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Programmable Input Delay
Schmitt Trigger Option on Single-Ended Inputs
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the ProASIC®3E Family
Clock Conditioning Circuit (CCC) and PLL
Six CCC Blocks, Each with an Integrated PLL
Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
Wide Input Frequency Range (1.5 MHz to 350 MHz)
SRAMs and FIFOs
Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations available)
True Dual-Port SRAM (except ×18)
24 SRAM and FIFO Configurations with Synchronous Operation up to 350 MHz
ARM® Processor Support in ProASIC3E FPGAs
M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available with or without Debug

Specifiche

Category	Integrated Circuits (ICs)EmbeddedFPGAs (Field Programmable Gate Array)	Series	ProASIC3E
Programmable	Not Verified	Total RAM Bits	110592
Number of I/O	147	Number of Gates	600000
Voltage - Supply	1.425V ~ 1.575V	Mounting Type	Surface Mount
Operating Temperature	-40°C ~ 100°C (TJ)	Base Product Number	A3PE600

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