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A3PE3000L-1PQG208I +BOM

FPGA with ProASIC®3EL technology, 3M gates, operating at 892.86MHz

Produttore:

MICROCHIP TECHNOLOGY INC
ProduttorePart #:

A3PE3000L-1PQG208I
Scheda dati:

A3PE3000L-1PQG208I Scheda dati (PDF)
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
HTS Code:

8542.39.00.01
Factory Lead Time:

52 Weeks
EDA/CAD Modelli:

Richiedi modelli CAD gratuiti per A3PE3000L-1PQG208I

A3PE3000L-1PQG208I Descrizione generale

The A3PE3000L-1PQG208I is a cutting-edge field-programmable gate array (FPGA) IC that belongs to the Microsemi SmartFusion2 family. With its impressive 3 million system gates and 295,000 logic elements, this high-density architecture is a versatile solution for a broad spectrum of industrial, communication, and automotive applications. Its quad flat package (QFP) with 208 pins ensures seamless integration onto printed circuit boards, making it a convenient choice for designers

Caratteristiche principali

Military Temperature Tested and Qualified

Each Device Tested from 55C to 125C

Firm-Error Immune

Not Susceptible to Neutron-Induced Configuration Loss

Low Power

Dramatic Reduction in Dynamic and Static Power

1.2 V to 1.5 V Core and I/O Voltage Support for Low Power

Low Power Consumption in Flash*Freeze Mode Allows for

Instantaneous Entry To / Exit From Low-Power Flash*Freeze

Mode

Supports Single-Voltage System Operation

Low-Impedance Switches

High Capacity

600 k to 3 M System Gates

Up to 504 kbits of True Dual-Port SRAM

Up to 620 User I/Os

Reprogrammable Flash Technology

130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

Live-at-Power-Up (LAPU) Level 0 Support

Single-Chip Solution

Retains Programmed Design when Powered Off

High Performance

350 MHz (1.5 V systems) and 250 MHz (1.2 V systems) System

Performance

3.3 V, 66 MHz, 66-Bit PCI (1.5 V systems) and 66 MHz, 32-Bit

PCI (1.2 V systems)

In-System Programming (ISP) and Security

Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532compliant)

FlashLock to Secure FPGA Contents

High-Performance Routing Hierarchy

Segmented, Hierarchical Routing and Clock Structure

High-Performance, Low-Skew Global Network

Architecture Supports Ultra-High Utilization

Specifiche

Part Life Cycle Code	Active	Reach Compliance Code	compliant
HTS Code	8542.39.00.01	Factory Lead Time	52 Weeks
JESD-30 Code	S-PQFP-G208	JESD-609 Code	e3
Length	28 mm	Moisture Sensitivity Level	3
Number of CLBs	75264	Number of Equivalent Gates	3000000
Number of Inputs	147	Number of Logic Cells	75264
Number of Outputs	147	Number of Terminals	208
Operating Temperature-Max	85 °C	Operating Temperature-Min	-40 °C
Organization	75264 CLBS, 3000000 GATES	Peak Reflow Temperature (Cel)	245
Power Supplies	1.2/1.5,1.2/3.3 V	Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY
Qualification Status	Not Qualified	Seated Height-Max	4.1 mm
Supply Voltage-Max	1.575 V	Supply Voltage-Min	1.14 V
Supply Voltage-Nom	1.2 V	Surface Mount	YES
Technology	CMOS	Temperature Grade	INDUSTRIAL
Terminal Finish	MATTE TIN	Terminal Form	GULL WING
Terminal Pitch	0.5 mm	Terminal Position	QUAD
Time@Peak Reflow Temperature-Max (s)	30	Width	28 mm

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Imballaggio

AVAQ determina e confeziona tutti i dispositivi in base ai requisiti di protezione contro le scariche elettrostatiche (ESD) e il livello di sensibilità all'umidità (MSL)..