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A3P030-QNG48 +BOM

Field Programmable Gate Array with 768 CLBs, 30000 Gates, operating at 350MHz using CMOS technology

Produttore:

MICROCHIP
ProduttorePart #:

A3P030-QNG48
Scheda dati:

A3P030-QNG48 Scheda dati (PDF)
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
ECCN Code:

EAR99
HTS Code:

8542.31.00.01
EDA/CAD Modelli:

Richiedi modelli CAD gratuiti per A3P030-QNG48

A3P030-QNG48 Descrizione generale

The A3P030-QNG48 electronic component is a versatile and powerful device designed for various applications in electronics. With its numerous logic elements and gates, this microcontroller or programmable logic device can handle complex tasks with ease. The A3P030 series is known for its reliability and efficiency, making it a popular choice among engineers and designers

Caratteristiche principali

High Capacity
15 k to 1 M System Gates
Up to 144 kbits of True Dual-Port SRAM
Up to 300 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design when Powered Off
High Performance
350 MHz System Performance
3.3 V, 66 MHz 64-Bit PCI†
In-System Programming (ISP) and Security
ISP Using On-Chip 128-Bit Advanced Encryption Standard (AES) Decryption (except ARM®-enabled ProASIC®3 devices) via JTAG (IEEE 1532–compliant)†
FlashLock® to Secure FPGA Contents
Low Power
Core Voltage for Low Power
Support for 1.5 V-Only Systems
Low-Impedance Flash Switches
High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure
Advanced I/O
700 Mbps DDR, LVDS-Capable I/Os (A3P250 and above)
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Wide Range Power Supply Voltage Support per JESD8-B, Allowing I/Os to Operate from 2.7 V to 3.6 V
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X† and LVCMOS 2.5 V / 5.0 V Input
Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-LVDS (A3P250 and above)
I/O Registers on Input, Output, and Enable Paths
Hot-Swappable and Cold Sparing I/Os‡
Programmable Output Slew Rate† and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the ProASIC3 Family
Clock Conditioning Circuit (CCC) and PLL†
Six CCC Blocks, One with an Integrated PLL
Configurable Phase-Shift, Multiply/Divide, Delay Capabilities and External Feedback
Wide Input Frequency Range (1.5 MHz to 350 MHz)
Embedded Memory†
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9, and ×18 organizations)†
True Dual-Port SRAM (except ×18)
ARM Processor Support in ProASIC3 FPGAs
M1 ProASIC3 Devices—ARM®Cortex™-M1 Soft Processor Available with or without Debug

Specifiche

Part Life Cycle Code	Active	Reach Compliance Code	compliant
ECCN Code	EAR99	HTS Code	8542.31.00.01
Factory Lead Time	40 Weeks	Clock Frequency-Max	350 MHz
JESD-30 Code	S-XQCC-N48	Length	6 mm
Moisture Sensitivity Level	3	Number of CLBs	768
Number of Equivalent Gates	30000	Number of Terminals	48
Operating Temperature-Max	85 °C	Operating Temperature-Min
Organization	768 CLBS, 30000 GATES	Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY
Qualification Status	Not Qualified	Supply Voltage-Max	1.575 V
Supply Voltage-Min	1.425 V	Supply Voltage-Nom	1.5 V
Surface Mount	YES	Technology	CMOS
Temperature Grade	COMMERCIAL	Terminal Form	NO LEAD
Terminal Pitch	0.4 mm	Terminal Position	QUAD
Width	6 mm

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