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Vedi Specifiche Tecniche

82845GE +BOM

Next-generation memory controller with compact design

Produttore:

INTEL
ProduttorePart #:

82845GE
Scheda dati:

82845GE Scheda dati (PDF)
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
HTS Code:

8542.31.00.01
JESD-30 Code:

S-PBGA-B478
EDA/CAD Modelli:

Richiedi modelli CAD gratuiti per 82845GE

82845GE Descrizione generale

This datasheet is for both the Intel® 82845GE Graphics and Memory Controller Hub (GMCH) and Intel® 82845PE Memory Controller Hub (MCH) components. The 82845GE GMCH is part of the Intel® 845GE chipset and the 82845PE MCH is part of the Intel® 845PE chipset. Each chipset contains two main components: GMCH (MCH) for the host bridge and I/O Controller Hub for the I/O subsystem. The GMCH (MCH) provides the processor interface, system memory interface, hub interface, and additional interfaces in an 845GE / 845PE chipset desktop platform. Both the 845GE chipset and 845PE chipset use the 82801DB ICH4 for the I/O Controller Hub.

Caratteristiche principali

Host Interface Support One processor in a mPGA478 package Hyper-Threading Technology support 400/533 MHz PSB (100/133 MHz bus clock) PSB Dynamic Bus Inversion on the data bus 32-bit addressing for access to 4 GB of memory space 8 deep In Order Queue AGTL+ On-die Termination System Memory Controller One 64-bit wide DDR SDRAM data channel Up to 2.0 GB of 266/333 MHz DDR SDRAM Bandwidth up to 2.7 GB/s (DDR333) 64-Mb, 128-Mb, 256-Mb, and 512-Mb SDRAM technologies Supports only x8 and x16 SDRAM devices with four banks Unbuffered, unregistered 184-pin non-ECC DDR SDRAM DIMMs only Two DDR DIMMs, single-sided and/or double-sided Does not support double-sided x16 DDR DIMMs JEDEC DDR DIMM specification configurations only Opportunistic refresh Up to 16, simultaneously open pages SPD (Serial Presence Detect) scheme for DIMM detection Suspend-to-RAM support using CKE Selective Command-Per-Clock (selective CPC) accesses Hub Interface Supports Hub Interface 1.5 266 MB/s point-to-point Hub Interface to the ICH4 66 MHz base clock 1.5 V operation AGP Interface Supports a single 1.5 V Accelerated Graphics Port Interface, Specification 2.0-compliant device Supports 1X/2X/4X data transfers and 2X/4X Fast Writes 32-deep AGP request queue AGP signals muxed with two Intel® DVO ports: Supports ADD cards (82845GE only)(Continue .)

Specifiche

Part Life Cycle Code	Active	Reach Compliance Code	compliant
HTS Code	8542.31.00.01	JESD-30 Code	S-PBGA-B478
Number of Terminals	478	Power Supplies	1.5 V
Qualification Status	Not Qualified	Supply Voltage-Nom	1.5 V
Surface Mount	YES	Technology	CMOS
Terminal Form	BALL	Terminal Pitch	1 mm
Terminal Position	BOTTOM

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